Performance of Generic and Recursive Pseudo Exhaustive Two-Pattern Generator

The main objective of this research is to design a Built-in self-test (BIST) technique based on pseudo-exhaustive testing. Two pattern test generator is used to provide high fault coverage. To provides fault coverage of detectable combinational faults with minimum number of test patterns than the conventional exhaustive test pattern generation, increases the speed of BIST and may posses minimum Hardware Utilization. A Built-in self-test (BIST) is a commonly used design technique that allows a circuit to test itself. Builtin self-test (BIST) technique based on pseudo-exhaustive testing, two pattern test generator is used to provide high fault coverage. It is widely known that a large class of physical defects cannot be modeled as stuck-at faults. For example, a transistor stuckopen fault in a CMOS circuit can convert a combinational circuit under test (CUT) into a sequential one, while a delay fault may cause circuit malfunction at clock speed, although it does not affect the steady-state operation. Detection of such faults requires two-pattern tests. It is proposed to design a BIST circuit for fault detection using pseudo exhaustive two pattern generator using minimum hardware utilization and increasing the speed of BIST.